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arichardson / immediate_format.md
Created April 17, 2026 21:26

8-Bit Floating-Point Immediate Specification (Uniform Scaling)

This specification defines an 8-bit immediate encoding designed for fine-grained memory allocation sizing. It utilizes a 3-bit exponent and a 5-bit mantissa to provide byte-granular precision for small allocations, scaling dynamically to standard cache-aligned sizes for medium allocations up to just under 4 KB.

1. Instruction Field Layout

The 8-bit immediate (imm8) is partitioned into two fields:

  • imm8[7:5] (3 bits): Exponent (Exp). Determines the implicit bit injection and the fixed left-shift amount.
  • imm8[4:0] (5 bits): Mantissa (M). Forms the base value.

2. Decoding Logic

@arichardson
arichardson / spec-riscv-immediates.csv
Created September 15, 2025 19:56
RISC-V SPEC immediate comparison frequency
We can make this file beautiful and searchable if this error is corrected: It looks like row 5 should actually have 44 columns, instead of 9 in line 4.
ImmediateValueDecimal,ImmediateValueHex,TotalFrequency,400.perlbench,401.bzip2,403.gcc,429.mcf,433.milc,444.namd,445.gobmk,447.dealII,450.soplex,453.povray,456.hmmer,458.sjeng,462.libquantum,464.h264ref,470.lbm,471.omnetpp,473.astar,482.sphinx3,483.xalancbmk,500.perlbench_r,502.gcc_r,505.mcf_r,508.namd_r,510.parest_r,511.povray_r,519.lbm_r,520.omnetpp_r,523.xalancbmk_r,525.x264_r,526.blender_r,531.deepsjeng_r,538.imagick_r,541.leela_r,544.nab_r,557.xz_r,997.specrand_fr,999.specrand_ir,imagevalidate_511-target,imagevalidate_525-target,imagevalidate_526-target,imagevalidate_538-target
1,0x1,"15,051",166,9,1243,2,44,10,204,143,47,148,33,76,7,201,6,40,0,30,428,285,7758,4,8,647,147,6,207,489,117,2194,29,228,16,18,53,0,0,2,2,2,2
2,0x2,"9,342",65,9,899,2,14,3,191,61,20,69,23,40,4,132,2,23,1,9,359,169,4440,2,3,468,66,2,122,256,118,1528,17,165,15,17,20,0,0,2,2,2,2
3,0x3,"7,339",65,6,737,0,18,1,267,37,10,34,20,51,4,58,0,12,0,5,129,179,4216,1,14,267,34,0,57,138,48,822,8,70,2,6,19,0,0,1,1,1,1
4,0x4,"3,849",37,10,297,0,9,
@arichardson
arichardson / riscv-cheri.diff
Last active September 5, 2025 04:55
Changes to isa-manual files for https://github.com/riscv/riscv-cheri/commit/3673a10dbbeed6bd4acfdc34dfc1119c291d9189
diff --git a/src/.asciidoctorconfig.adoc b/src/.asciidoctorconfig.adoc
new file mode 100644
index 00000000..9a5b643c
--- /dev/null
+++ b/src/.asciidoctorconfig.adoc
@@ -0,0 +1,2 @@
+:cheri_v9_annotations: 1
+include::{asciidoctorconfigdir}/cheri/attributes-standalone.adoc[]
diff --git a/src/a-st-ext.adoc b/src/a-st-ext.adoc
index 100f004d..0b9d6711 100644
@arichardson
arichardson / shadd.diff
Last active August 19, 2025 17:07
"Fake" CHERI LLVM support for shift-add instruction (static code size experiment)
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
index 8b0bfd05d277..e45c7eabccdf 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXCheri.td
@@ -410,6 +410,20 @@ def : InstAlias<"csetboundsimm $cd, $cs1, $imm",
(CSetBoundsImm GPCR:$cd, GPCR:$cs1, uimm12:$imm), 0>;
}
+let Predicates = [HasCheri, HasStdExtZba] in {
+def CSH1ADD : Cheri_rr<0x31, "csh1add", GPCR, GPCR, GPR>;
@arichardson
arichardson / analyze_instr_freq.py
Created August 19, 2025 15:21
Count number of times each RISC-V instruction is emitted
#!/usr/bin/env python
# -*- coding: utf-8 -*-
#
# Description:
# This script recursively finds all RISC-V ELF files in a specified directory
# and categorizes them into "purecap" (CHERI-enabled) and "integer" buckets
# based on the EF_RISCV_CHERIABI flag in the ELF header. It only includes
# executables and shared libraries, ignoring object files. It counts every
# assembly instruction mnemonic and provides grand totals and optional CSV
# reports for each bucket. It correctly handles symbolic links to avoid
@arichardson
arichardson / cheri-spec.diff
Created February 19, 2025 21:54
diff --git a/sail_latex_riscv/commands.tex b/sail_latex_riscv/commands.tex
index 80a14033..6ddc4805 100644
--- a/sail_latex_riscv/commands.tex
+++ b/sail_latex_riscv/commands.tex
@@ -33,8 +33,7 @@
\newcommand{\sailRISCVvalundefinedUnit}{\saildoclabelled{sailRISCVzundefinedzyunit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzundefined_unitd751910db26c6cf7ec5d02a503ad4f9e.tex}}}}
-\newcommand{\sailRISCVvaledivInt}{\saildoclabelled{sailRISCVzedivzyint}{\saildocval{ Euclidean division
-
@arichardson
arichardson / cheri-specification.diff
Last active February 19, 2025 21:28
diff --git a/sail_latex_riscv/commands.tex b/sail_latex_riscv/commands.tex
index c98a894e..6ddc4805 100644
--- a/sail_latex_riscv/commands.tex
+++ b/sail_latex_riscv/commands.tex
@@ -33,8 +33,7 @@
\newcommand{\sailRISCVvalundefinedUnit}{\saildoclabelled{sailRISCVzundefinedzyunit}{\saildocval{}{\lstinputlisting[language=sail]{sail_latex_riscv/valzundefined_unitd751910db26c6cf7ec5d02a503ad4f9e.tex}}}}
-\newcommand{\sailRISCVvaledivInt}{\saildoclabelled{sailRISCVzedivzyint}{\saildocval{ Euclidean division
-
@arichardson
arichardson / gist:fc02b284098af968d949787cadd2e610
Created September 19, 2020 15:17
buildworld failure
===> usr.bin/column (includes)
===> usr.bin/comm (includes)
===> tests/sys/pjdfstest/tests/mkfifo (includes)
===> usr.bin/col/tests (includes)
===> cddl/usr.sbin/zhack (includes)
===> usr.bin/cmp/tests (includes)
===> libexec/rpc.rquotad (includes)
===> libexec/rpc.rstatd (includes)
===> usr.sbin/cron/crontab (includes)
===> libexec/rc/rc.d (includes)
@arichardson
arichardson / Broken LLVM IR
Created February 20, 2020 10:41
; ModuleID = 'reproducer.c'
source_filename = "reproducer.c"
target datalayout = "E-m:e-pf200:128:128:128:64-i8:8:32-i16:16:32-i64:64-n32:64-S128-A200-P200-G200"
target triple = "mips64c128-unknown-freebsd13.0-purecap"
%struct.explore = type { i32, i32, i32, i32 }
%struct._ns_dtab = type { i8 addrspace(200)*, i32 (i8 addrspace(200)*, i8 addrspace(200)*, i8 addrspace(200)*) addrspace(200)*, i8 addrspace(200)* }
%struct.addrinfo = type { i32, i32, i32, i32, i32, i8 addrspace(200)*, %struct.sockaddr addrspace(200)*, %struct.addrinfo addrspace(200)* }
%struct.sockaddr = type { i8, i8, [14 x i8] }
%struct.in6_ndireq = type { [16 x i8], %struct.nd_ifinfo }
@arichardson
arichardson / backtrace
Created October 25, 2018 15:01
_cheri_capability_build_user_data+0x54 (?,?,?,?) ra ffffffff8072fab4 sp c000000013e9f470 sz 16
cheri_syscall_authorize+0x1454 (?,?,?,?) ra ffffffff803c6a7c sp c000000013e9f480 sz 128
kern_execve+0x1424 (?,?,?,?) ra 0 sp c000000013e9f500 sz 0